1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a structure of a static random access memory (SRAM) cell operating at low power and low voltage and a method for fabricating the same.
2. Discussion of the Related Art
A general FULL-CMOS SRAM has disadvantages in that it includes two PMOS transistors and 4 NMOS transistors, and occupies a large area. Research and development has been directed to increasing packing density of a memory chip by minimizing an area occupied by an SRAM cell.
A structure of a SRAM cell will be discussed below.
FIG. 1 is a layout of a conventional CMOS SRAM cell. As shown in FIG. 1, a twin-well CMOS process using single-level polysilicon and double-level aluminum is implemented on an n-type substrate for a general SRAM chip. A gate in an NMOS device is 0.8 .mu.m long, and a gate in a PMOS device is 1.2 .mu.m long. A lightly doped drain (LDD) structure is used in an NMOS device to prevent hot carrier generation.
A gate oxide layer is 20 nm thick, and a threshold voltage of a PMOS device is -0.5V, while a threshold voltage of an NMOS device is 0.5V.
In the SRAM cell shown in FIG. 1, each first aluminum layer 11 is 1.3 .mu.m wide and a distance between each of the first aluminum layers 11 is 1.0 .mu.m. Each second aluminum layer 12 is 1.1 .mu.m wide and a distance between each of the second aluminum layers 12 is 0.8 .mu.m.
The first aluminum layers 11 are used as a word line and a Vcc line that crosses arrays of SRAM cells.
In the SRAM cell, two metal lines of the second aluminum layer 12 are used as ground lines (Vss lines), and two other metal lines are used as bit lines or bit bar lines (B/L or B/L).
Bit lines in adjacent cells are separated by ground lines (Vss) in order to prevent the reduction of cell signals due to noise from capacitive coupling during a READ operation.
FIG. 2 is an equivalent circuit diagram of the conventional SRAM cell. As shown in FIG. 2, it takes six transistors to form a CMOS SRAM cell that uses a PMOS transistor as a loading device.
A source S1 of a first transistor Q1 is connected to the bit line, and a source S2 of a second transistor Q2 is connected to the bit bar line B/L.
Sources S6 and S5 of a sixth transistor Q6 and a fifth transistor Q5 (which is a PMOS transistor used as a loading device), respectively, are connected to the Vcc line.
A drain D5 of the fifth transistor Q5 is connected to a drain D3 of the third transistor Q3. A source S3 of a third transistor Q3 is connected to a Vss line.
A drain D6 of the sixth transistor Q6 is connected to a drain D4 of the fourth transistor Q4, and a source S4 of the fourth transistor Q4 is connected to a Vss line.
A gate G3 of the third transistor Q3 and a gate G5 of the fifth transistor Q5 are connected to each other. A gate G4 of the fourth transistor Q4 and a gate G6 of the sixth transistor Q6 are connected to each other.
A drain D1 of the first transistor Q1 is connected to gates G4 and G6 of the fourth and sixth transistors Q4 and Q6, respectively. A drain D2 of the second transistor Q2 is connected to the gates G3 and G5 of the third and fifth transistors Q3 and Q5, respectively.
A layout of the conventional SRAM cell will be described below.
FIG. 3 shows a layout of the conventional SRAM cell of FIG. 1 including elements of the SRAM cell of FIG. 2. As shown in FIG. 3, a first gate line 31 is formed in a first direction, and a second gate line 32 is formed at a right angle to the first gate line 31 and offset from the first gate line 31. A third gate line 33 is formed facing the second gate line 32.
The first gate line 31 is used as the gates G1 and G2 of the first and second transistors Q1 and Q2, and the second gate line 32 is used as the gates G3 and G5 of the third and fifth transistors Q3 and Q5. The third gate line 33 is used as gates G4 and G6 of the fourth and sixth transistors Q4 and Q6.
A first metal line 34 is formed to electrically connect the drain D5 of the fifth transistor Q5 to the drain D3 of the third Q3. A second metal line 35 is formed to electrically connect the drain D6 of the sixth transistor Q6 to the drain D4 of the fourth transistor Q4.
The second and third gate lines 32 and 33 are connected through contact holes to the second and first metal lines 35 and 34, respectively.
Reference numerals 36a, 36b, 36c, and 36d designate active regions of the transistors Q1-Q6.
The SRAM cell is formed on an n-type substrate. A p-type well is formed to form two PMOS transistors (the fifth and sixth transistors Q5 and Q6) used as a double loading device. Four NMOS transistors are formed in an n-type well.
The structure of the conventional SRAM cell has the following problems. Since four metal lines are needed, packing density of SRAM cells is low, and memory chip size is large. Further, since a distance between p well and n well needed for isolation is large, the packing density is low. Furthermore, since there are different Vss lines in the SRAM cell, ground line resistances of transistors connected to the Vss lines are also different.